Marvell Senior System Validation Engineer 

United States, California 

944638411

Job Responsibilities: · SOC, Sub system & Block verification activities - should have participated in successful completion of SOC/Subsys projects across all phases from SOC/Subsys/Block Specification to Silicon. · Responsible for complete SOC/Subsys/Block verification activities like - develop verification architecture and verification plan, develop UVM based testbench, Integrate in-house verification components + complex VIP’s ( ARM, Cadence, Synopsys, etc), develop test cases (UVM & assembly), verify and do coverage analysis in RTL and gate level design. · Work effectively with a global team and be self-motivated to manage deliverables · Communicate clearly both verbally and in writing.

Technical Experience: · Bachelor’s degree in CS/EE with 8–12 years of relevant experience, or Master degree in CS/EE with 8–10 years of relevant experience · Strong background in IP, Subsystem and SoC verification, including methodology and testbench development · Proficient in hardware verification languages such as Verilog, SystemVerilog, UVM, and C/C++ · Solid understanding of verification methodologies: object-oriented programming, white-box/black-box testing, directed/random testing, coverage analysis, and gate-level simulations · Experience in Unix/Linux environments; scripting skills in Shell, Perl, or Python are a plus · Strong analytical and problem-solving skills · Ability to manage multiple tasks in a fast-paced environment · Excellent communication, interpersonal, and teamwork skills · Capable of interfacing effectively at all levels within and outside the organization · Proactive in participating in problem-solving and quality improvement initiatives