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The Role:
In this role you will:- Lead ASIC-to-FPGA conversion projects, including RTL modification and optimization- Architect and implement multi-FPGA partitioning solutions- Design and debug high-speed interfaces including Ethernet, PCIe, and DDR- Debug hardware issues using logic analyzers and oscilloscopes- Create and release FPGAs through the development phases of uArchitecture-RTL Design-Physical Implementation-Timing Closure–Simulation Validation– Lab Based Silicon Validation
Export Control Requirement:
- Bachelor's degree in Electrical Engineering or related discipline
- 7+ years in FPGA design & implementation
- Proficiency in Verilog or SystemVerilog
- Experience with at least one major FPGA development tool (e.g., Xilinx Vivado, Intel Quartus)
- Demonstrated ability to design and implement digital logic systems using FPGAs
- Familiarity with timing analysis and constraints
- Basic understanding of high-speed interfaces (e.g., PCIe, DDR)
- Experience with hardware debugging tools (e.g., logic analyzers, oscilloscopes)
- Record of success in the design, test, delivery, support of multiple FPGAs shipping to customers
- Experience with uArchitecture, RTL coding, FPGA optimization for timing & power, simulation, and validation
- Experience with HLS
- Experience with Computer Networking Systems from Layer2 to Layer4
- Experience with TCP/IP Systems
- Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2 / DVB-C, or similar broadband wireless standards
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