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Apple Digital Circuit Design Engineer United States, California, San Diego 938463096
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- Master’s degree or foreign equivalent in Electrical Engineering or related field.
- Experience and/or education must include:
- Understanding VLSI design process in sub-micron process nodes and applying in stdcell and memory QA.
- Working with vendor and circuit designers for Virtuoso library releases, including deliver schematics, symbol, and layout.
- Using vendor tools including Cadece Liberate and Synopsys PrimeLib to characterize stdcell circuits and build timing, power, and noise models.
- Using vendor tools including Cadence ncverilog or xcelium to simulate Verilog models for stdcell and memory.
- Using formal verification tools including Cadence Conformal and Synopsys Formality to verify Verilog models for stdcell and memory.
- Developing Python scripts for daily tasks, including postprocessing and QA data.
- Developing and maintaining automation flows for stdcell and memory IPs.
- Using Matlab and Octave to analyze circuit design/simulation data for QA.
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