The application window is expected to close on 1/27/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Your Impact
You are responsible for ensuring the development, testing, and quality analysis of library IP used for ASIC implementation. Additional responsibilities are:
- Re-characterization of standard cell libraries to various Process/Voltage/Temperature parameters
- Develop and perform quality analysis checks on library timing/power values, and checks on consistency across views e.g. (Verilog, LEF, GDS, etc)
- Intall, test, maintain and release internal 3rd party IP
- Memory macro compilation, testing, and release
Minimum Qualifications:
- Typically a Bachelor’s + 7 years of related experience, or Masters + 4 years of related experience, or PHD + 1 year of related experience.
- 7nm and below
- Prior experience with CAD methodologies from Cadence, Synopsys and/or Mentor
- Experience scripting/coding with TCL and Python/Perl
Preferred Qualifications
- Experience with Finfet technology
- Experience analyzing data and presenting in front of an audience