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Apple Digital Integration & Timing Engineer United States, California, Sunnyvale 922267699
06.06.2024
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Description
As a Digital Integration & Timing Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators and multiple ARM-based sub-systems. You will have the opportunity to work closely with SoC architects and IP developers to develop SoCs that meet Apple devices' power, performance, and area goals. You will help define the processes, methods, and tools for designing and implementing these large, complex SoCs. Collaboration with multi-disciplinary groups will be needed to make sure designs are delivered on time and with the highest quality by incorporating accurate checks at every stage of the design process. In this highly visible role, you will be at the center of the ASIC creation effort, interfacing with all disciplines, with a critical impact on getting leading-edge products out to delight millions of customers.- Full chip and block-level timing constraint and closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).- Deploy and enhance methodology and flows related to timing constraint verification and timing closure.- Generation of consistent block and full chip timing constraints.- Support digital chip integration work and flows.- Execute low power design and physical synthesis techniques, deploying knowledge of UPF and power intent verification.- Collaborate with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve the tape out success on designs - generally bridging everything between the RTL and PD worlds.
Key Qualifications
- BS and 3+ years of relevant industry experience.
- Knowledge of the entire ASIC design flow from RTL integration through synthesis, static timing analysis, scripting, P&R to tapeout.
- Expertise in STA tools and flow.
- UPF usage for power and voltage islands.
- Hands-on experience in timing/SDC constraints generation and management.
- Knowledge of timing corners, operating modes, process variations, and signal integrity-related issues.
- Proficient in scripting languages (TCL and PERL).
- Logic synthesis execution for efficient PPA using physically aware techniques in single-digit process nodes using Design Compiler, Fusion Compiler &/or Genus.
- Proficient in the closure of end-to-end logic equivalence (FV, LEC) with functional ECOs in the mix.
- Familiarity with DFT and backend related methodologies and tools.
- Proficient with RTL Verilog/VHDL.
- Knowledge of digital top integration flows/methodology/checks.
- Experience with script-based tool automation, API’s and scripting languages for EDA tools, such as; Design Compiler, Genus, PrimeTime, etc.
Education & Experience
BS and 3+ years of relevant industry experience.
Additional Requirements
- Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $138,900 and $256,500, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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