Intel Analog Mixed Signal IO Clocking Design Engineer 

India, Karnataka, Bengaluru 

912619034

Develops and drives analog and mixed signal IP architectures, low jitter clocking circuit implementation/verification, signal processing algorithms, and calibration algorithms for SoC independent analog mixed signal (AMS) IPs. Performs top down architectural analysis of AMS systems and conducts transistor level feasibility study for various AMS circuits. Drives analog and mixed signal functionality, connectivity, and configuration. Enhances system performance using digitally assisted analog techniques and optimum partitioning of analog and digital circuits. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for analog and mixed signal IP. Invents, conceptualizes, and specifies microarchitecture and architectural features for next generation to deliver optimized analog and mixed signal IP for multiple segments from high performance computing to extreme low power products. Develops modeling scenarios and modeling for new architectures/features for analog and mixed signal IPs. Performs modeling simulations, estimation, and optimization for power and area and conducts analysis of test results using advanced statistics and data predictions for benchmarking and determining areas for improvement. Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints. Reviews, challenges, and influences cross functional roadmaps and defines technology targets for future analog and mixed signal IPs. Collaborates with IP design engineers and IP verification engineers to design and validate SoC independent IPs. Supports SoC architects, SoC design engineers, and SoC verification engineers in selecting, configuring, integrating, and validating SoCs that utilize analog and mixed signal IPs.

• Master's degree in Electronics Engineering, Electrical Engineering or related STEM degree with at least 6+ years' experience in semiconductor IO/SERDES/memory/Clocking design OR
• Bachelor's degree in Electrical/Electronics Engineering or related STEM degree with at least 9+ years in semiconductor memory design.

• Expertise in Serdes/custom memory IO design including LPDDR, HBM,GDDR, CXL.mem, etc.
• System Level simulation knowledge and experience in Matlab/Serdes Tool box.
• Phase Locked Loops (PLL)s, PLL sub-circuits such as Phase Frequency Detectors, Charge Pumps, High-Speed Clock Dividers, Time-to-Digital Converters (TDC) and Digital-to-Time Converters (DTC)
• High performance Oscillators, electromagnetic elements such as inductors, transformers, transmission lines for wireline and wireless applications.
• Analog front-ends and equalizers utilizing BW extension techniques, high-speed ADCs and DACs.
• Analog and digital filter design, digital signal processing (DSP) and digitally assistance for analog design
• HSIO serdes, equalization, channel compensation tradeoff design.
• EDA tool suite used for Memory, IO, SOC IP development, signoff, QA, and integration.
• Multi-generation product design experience in DRAM, Flash, or SRAM is required.
• EDA tool suite used for Memory, IO, SOC IP development, signoff, QA, and integration.
• Multi-generation product design experience in DRAM, Flash, or SRAM is required.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits