As a lead verification engineer with knowledge of various multimedia protocols, you will make valuable contributions to a team tasked with verifying the functional correctness of SOCs.
Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules.
Engineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy.
Work with the Emulation/FPGA team to understand the various verification collaterals required for driving stimulus at the board level.
Collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development.
Senior engineers are also encouraged to support junior members.
Required Skills and Experience :
10+ years of proven experience in working on SoC multimedia verification environments.
Hands-on with display, audio, video, camera protocols like MIPI, HDMI, DP, eDP, etc
Experience with the system MMU and understanding of the fundamentals of Arm system architectures
Knowledge of assembly language (preferably ARM), C/C++ and hardware verification languages (e.g. SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.) and
Experience in one or more of various verification methodologies – UVM/OVM, formal, low power.
Exposure to all stages of verification: requirements collection, creation of test plans, testbench implementation, test cases development, documentation and support.
Ability to work under time-scale pressure and meet ambitious targets without compromising on quality
Experience with various front-end verification tools - Dynamic simulation tools, Static Simulation tools, UPF, and Debuggers.
“Nice To Have” Skills and Experience :
Possess knowledge of object-oriented programming concepts
Practical experience of working on Processor-based system design