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Apple CPU Cache RTL Architect United States, Massachusetts, Waltham 902948063
06.06.2024
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Description
As a CPU RTL Architect, you will own or participate in the following: - Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification. - RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals.
Key Qualifications
- Minimum BS and 10+ years of relevant industry experience
- Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas:
- - Coherence protocols and interconnects
- - High performance (low latency, high bandwidth) design techniques
- - Memory subsystem queuing, scheduling; starvation and deadlock avoidance
- - SRAM design basics
- - Multiple clock/power domains and power management strategies
- - Prefetchers, replacement policies
- - Debug capabilities
- - DFT strategies
- - Error detection and correction
- Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools.
- Knowledge of logic design principles along with timing and power implications
- Understanding of low power microarchitecture techniques
- Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
- Experience in C or C++ programming
- Experience using an interpretive language such as Perl or Python
Education & Experience
Minimum BS and 10+ years of relevant industry experience
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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