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Google ASIC AI/ML Design Engineer Silicon India, Karnataka, Bengaluru 900766941
29.07.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Science Engineering, or equivalent practical experience.
- 4 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
- 4 years experience in ARM-based SoCs, interconnects and ASIC methodology.
Preferred qualifications:
- Master’s degree in Electrical Engineering or Computer Engineering.
- 4 years of experience with IP design for clocking, interconnects, and peripherals.
- Experience in scripting language such as Python or Perl.
- Experience with methodologies for low power estimation, timing closure, and synthesis.
- Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).
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