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Amazon Compiler Engineer II - Machine Learning Annapurna Labs 
United States, California, Cupertino 
900181760

05.08.2024
DESCRIPTION

In this role as a ML Compiler engineer, you'll be instrumental in designing, developing, and optimizing features for our compiler. Your responsibilities will involve tackling crucial challenges alongside a talented engineering team, contributing to leading-edge design and research in compiler technology and deep-learning systems software. Additionally, you'll collaborate closely with cross-functional team members from the Runtime, Frameworks, and Hardware teams to ensure system-wide performance optimization.As part of the Backend team, you'll play a significant role in designing and developing various aspects of our system. This includes but is not limited to instruction scheduling, memory allocation, data transfer optimization, graph partitioning, parallel programing, code generation, Instruction Set Architectures, new hardware bring-up, and hardware-software co-design.Key job responsibilities
Solve challenging technical problems, often ones not solved before, at every layer of the stack.
Design, implement, test, deploy and maintain innovative software solutions to transform service performance, durability, cost, and security.
A day in the life
As you design and code solutions to help our team drive efficiencies in software architecture, you’ll create metrics, implement automation and other improvements, and resolve the root cause of software defects. You’ll also:
Participate in design discussions, code review, and communicate with internal and external stakeholders.Work in a startup-like development environment, where you’re always working on the most important stuff.


BASIC QUALIFICATIONS

- B.S. or M.S. in computer science or related field
- Proficiency with 1 or more of the following programming languages: C++ (preferred), Python
- 3+ years of non-internship professional software development experience
- 2+ years of experience developing compiler optimization, graph-theory, hardware bring-up, FPGA placement and routing algorithms, or hardware resource management