Texas Instruments Resolution Enhancement Techniques Process Development Engineer 

United States, Texas, Dallas 

897817085

As a Resolution Enhancement Techniques (RET) Engineer, you'll architect new TI products and make our customers' visions a reality. You'll define, design, model, implement, and document analog, digital, and RF integrated circuits (ICs). Responsibilities will include, but are not limited to:

• Partnering with design, process engineering and process integration teams to develop mutually agreeable design specifications for manufacturing processes for advanced analog nodes
• Developing/improving mask/lithography/etch processes for next node analog nodes through photolithographic simulation and on mask/wafer verification
• Data collection, simulation and verification of optical proximity correction (OPC) models and recipes
• Partnering with internal/external fabs to transfer processes for advanced analog nodes
• Troubleshooting photolithographic patterning/alignment related issues for all fabs within TI

Responsibilities include:

• Drive process and device improvements through characterization, test, design of experiments, data analysis and simulation
• Work with multiple process, integration, reliability, packaging and test engineers to achieve these goals
• Work closely with the product groups to identify and optimize the resonator performance to meet critical final device parameters to enable game changing products in the market

Minimum requirements:

• Masters in Electrical Engineering, Physics, Computer Science, Chemistry or related degree
• 10 + years experience in semiconductor photolithography and/or OPC development
• FEOL lithography & OPC expertise for 45nm, 28nm, 22nm and 20nm processing nodes

Preferred qualifications:

• Expertise in double patterning and test structure requirements to validate OPC solutions
• Strong knowledge/understanding of advanced front end of the line (FEOL) lithography processes, lithography simulation techniques, mask making and OPC techniques used in semiconductor manufacturing and process development
• FEOL integration experience
• Familiarity with physical layout (gds/oas). Knowledge of litho/OPC test pattern design and layout execution using test pattern generators and use of layout software like Virtuoso, KLayout
• Programming experience in Unix environment
• Understanding of OPC pattern validation methodologies and process window assessment techniques like KLA’s Process Window Qualification (PWQ)
• Demonstrated strong analytical and problem solving skills
• Strong verbal and written communication skills
• Ability to work in teams and collaborate effectively with people in different functions
• Strong time management skills that enable on-time project delivery
• Demonstrated ability to build strong, influential relationships
• Ability to work effectively in a fast-paced and rapidly changing environment
• Ability to take the initiative and drive for results