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About the Role:
In this role you will Perform implementation of High performance block level physical design from RTL to GDS to create a design database that is ready formanufacturing. Conduct all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noiseanalysis. Conductverification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Achieving final convergence. Analyse results and make recommendations for current and future product architecture. Possess expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools(Cadence/Synopsys/Mentor/Ansys).Optimizeand converge design to meet and improve product-level parameters such as power, frequency, and area.
Participate in the development and improvement of physical design methodologies and flow automation.
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