Intel Senior Device Integration Engineer 

United States, Arizona, Phoenix 

895087463

Job Description:

The Device Integration engineer's responsibilities include:

• Own engineering projects to execute HVM yield roadmap, device targeting and attain performance targets.
• Collaborate with Technology Development team to develop new device technology, customize device architecture per customer request and import to production fabs.
• Participate or lead cross-organizational team of engineers to identify root cause of device-related yield/performance issues and define mitigation plan to meet committed production yield/performance targets.
• Own NPI (New Product Introduction) in production fabs and perform device-related process optimization to meet foundry customers product specifications and requirements.
• Develop a model to predict device performance accurately in early-to-mid stage of Si progression and drive systematic solution to maintain baseline device performance.
• Work with Process Integration engineers to drive process simplification and implement cost reduction engineering opportunities in line.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Physics or Materials Science major. Other related science and engineering degrees can be considered based on industry experience with 6+ years of experience in advanced node semiconductor industry in Device Integration.
• Experience in FinFET technology development or high-volume manufacturing.
• Experience with Device Physics and hands-on application in real-world fab environment.

Preferred Qualifications:

• Advanced degree (Master's with 4+ years of experience or Ph.D. with 2+ years of experience) in Electrical Engineering, Physics or Materials Science major.
• Experience in project/program management and/or task force team lead.
• Demonstrated interpersonal skills including influencing, engaging and motivating.
• Experience in serving external Foundry customers through technical interactions.
• Experience in GAA (Gate-All-Around) technology architecture.
• Experience in new semiconductor technology development.
• Experience with FEOL (Front-End-Of-Line) Integration teams including Fin, Poly, Source/Drain and Gate segments on device performance improvement and targeting with technical understanding on how FEOL process changes impact device parameters.
• Previous related work experience in a semiconductor foundry preferred

Experienced HireShift 1 (United States of America)US, Arizona, Phoenix
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: