In this job you will be responsible for translating custom mixed-signal circuit schematics into efficient SystemVerilog behavioral models for high level simulations. You will closely interact with circuit design teams to understand the details of custom circuits, and with DV teams to craft hooks for effective verification. You will run simulations and formal equivalence tools to ensure that the model matches closely with the custom circuits. You will code targeted checks within these representative models to ensure that the circuits are used as intended. You will write scripts and simple tools for automating repetitive tasks or performing calculations.