Broadcom Digital Design Verification Engineer 

United States, California, San Jose 

885640613

Broadcom is looking for a senior level Digital Design Verification engineer. In this highly visible role you will be working on various ASIC products for the next generation of optical and electrical data center connectivity products.

Qualifications include:

• BSc in Electrical Engineering or Computer Engineering with 8+ years of experience in ASIC Design Verification or MS in Electrical Engineering or Computer Engineering with 6+ years of experience in ASIC Design Verification

• Deep knowledge about System Verilog, UVM and verification coverage matrix

• Experienced in developing checker, scoreboard & writing assertions.

• Prior experience and knowledge of ARM core, APB/AHB bus protocol, Serial peripherals (eg: I2C, SPI), SRAM integration

• Familiarity with generating randomized vectors for analog and digital behavioral model verification.

• Hands-on knowledge of standard industry EDA tools - Synopsys/Cadence.

• Working knowledge of Assembly, C, and C++ languages and use in embedded systems

• Experienced with GLS with & without parasitic annotated simulations.

Highly Desired Qualifications:

• Strong written and verbal communication skills, with the specific ability to speak to various technical and management levels.

• Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results.

• Excellent time and task management, and interpersonal skills.

Compensation and Benefits

The annual base salary range for this position is $106,800 - $178,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.