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Apple Design Verification Engineer United States, Oregon, Beaverton 87279145
06.06.2024
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Description
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. Develop block, IP and SoC level test-benches. Track and report DV progress using a variety of metrics, including bugs and coverage. Develop IP simulation environment, and work closely with analog team to ensure overall bug-free IP designs.
Key Qualifications
- Deep proven understanding of SystemVerilog test-bench language and UVM
- Shown experience developing scalable and portable test-benches
- Validated experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations
- Experience with IP verification methodology
- Solid understanding of UVM knowledge, C/C++ knowledge
- Significant experience with DDR PHY or Controller
- Deep knowledge of one of the scripting languages: Python, Perl, TCL
- Deep knowledge of formal verification methodology
Education & Experience
BS degree in technical discipline with minimum 3 years of confirmed experience.
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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