Marvell Principal Engineer Hardware Validation 

Vietnam, Ho Chi Minh City 

865615378

What You Can Expect

• Design and implement advanced DFT architectures to ensure comprehensive testability in complex ASIC/VLSI designs.
• Develop and optimize test methodologies such as JTAG, SCAN, MBIST, and Boundary Scan (BScan) for maximum efficiency.
• Collaborate with cross-functional teams including RTL design, verification, backend, and post-silicon teams to ensure seamless integration.
• Conduct structural and functional verification of DFT features using industry-leading EDA tools (e.g., Cadence, Synopsys, Siemens (MentorGraphics).
• Perform post-silicon validation and debugging, analyzing silicon test results to refine DFT strategies for production.
• Enhance automation and workflow efficiency by implementingadvanced DFT methodologies and integrationtools.
• Support low-power design techniques, ensuring efficient DFT integration for power-sensitive applications.

What We're Looking For

• 6+ years of proven experience in ASIC/VLSIDFTdesign and verification.
• Bachelor’s degree in computer science, Electrical Engineering, or related fields.
• Extensive hands-on experience with EDA tools (e.g., Cadence, Synopsys,Siemens (Mentor Graphics).
• Deep understanding of DFT methodologies, including JTAG, SCAN, MBIST, and BScan.
• Strong debugging skills to identify and resolve design and test issues.
• Experience withSpyglass Lint,CDC and RDC (advantage).
• Familiarity with I/O and package design principles (advantage).
• Experience with low-power design techniques and methodologies (advantage).
• Excellent analytical and problem-solving skills, with the ability to work independently and manage multiple tasks.