Microsoft Hardware Engineer II - Design Verification 

United States, Washington 

860774039

You will develop the infrastructure for next-generation SDN accelerators which can do arbitrary packet manipulations, provide network security, enhance connection establishment performance, and improve performance with Remote Direct Memory Access (RDMA) and custom network protocols. You should be able to drive projects with both hardware and software teams, both inside and outside of Microsoft.

Required Qualifications:

• Bachelor's Degree in Computer Science or related technical field AND 2+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python

  • OR equivalent experience.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Additional / Preferred Qualifcations:

• 5+ years technical experience in hardware design verification, verification methodologies, and system Verilog.
  • OR Bachelor's Degree in Electrical Engineering, Computer Science, Computer Engineering, Information Technology, or related field AND 2+ years technical experience in network design, development, and automation.
  • OR Master's Degree in Electrical Engineering, Computer Science, Information Technology, or related field AND 1+ years technical experience in network design, development, and automation
  • OR Doctorate Degree in Electrical Engineering, Computer Science, Computer Engineering, Information Technology, or related field.

• Understanding of constrained random verification principles and experience in writing comprehensive test plans.
• 7+ years of project experience verifying several designs at unit and system level.
• Deep understanding of system Verilog constraints, functional coverage, and assertions.
• Familiarity with formal verification.
• Programming skills in C/C++, System Verilog, Assembly, and knowledge of advanced computer architecture.
• Communication skills, team player, self-driven and problem-solving ability.
• Experience in scripting languages such as Python and PowerShell.
• Knowledge of networking fundamentals, including protocols such as IPV4, IPV6, TCP, UDP, DTLS, VXLAN, NVGRE, ICMP, ARP, among others.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

• Build scalable constrained random verification environment in system Verilog using prevalent verification methodologies.
• Create comprehensive test plans to address functional scenarios in discussions with the software and hardware design teams.
• Execute the test plan by adding testcases and tracking verification through coverage driven metrices.
• Create and enhance verification environment by adding sequences, constraints, assertions, and functional coverage.
• Scripts to automate and maintain execution of test suits to support continuous integration (CI) and continuous development (CD) flow.
• Apply Agile development methodologies such as hosting code reviews, sprint planning, frequent deployment to cloud, and iterative development of features.
• Handle occasional on-call responsibilities for addressing hardware issues reported by our customers.
• Embody our