Intel Senior Defect Reduction Engineer 

United States, Arizona, Phoenix 

859371684

Senior Defect Reduction Engineer’s responsibilities include (but not limited to):

• Collaborate with Technology Development team and Process Integration team to import and setup new technology to production fabs across the globe.
• Work with Process Integration teams, Yield Analysis team and FSM Yield teams to lead fast paced yield ramp-up in high-volume manufacturing phases.
• Identify systematic defect issues in line and design mitigation actions in defined timeline to meet committed production yield targets.
• Own engineering projects to eliminate systematic defect issues with Process Integration teams, Yield Analysis team, and Fab module teams.
• Work with Defect Control team to execute production line inspection strategy to protect yield and quality at maximum productivity and lowest cost.
• Engineering support for technical interactions with internal and external customers.

• technique with strong self-initiative and self-learning capabilities
• Ability to work with multi-functional, multi-cultural teams.
• Must demonstrate solid communication skills.

MinimumQualifications:

• Bachelor's Degree in Electrical Engineering, Physics, Chemistry, Materials Science or in a STEM related Field.
• 5+ years' experience in advanced node semiconductor industry in Defect engineering.
• Experience in identifying defect mechanism, assessing its yield impact and improving D0.
• Experience in FinFET technology development or high-volume manufacturing with hands-on knowledge of FinFET technology process flow to analyze systematic defect sources and set mitigation actions.
• Experience in developing improvement projects at module level and collaborate with module teams to improve process for reduced defectivity and improved yield.
• Experience in layout-sensitive defect weak points and how OPC works.
• Experience with module tool impacts to defects, inline parametrics and yield through PM life while understanding upstream and downstream impacts to other tools.

PreferredQualifications:

• Advanceddegree (Master's or Ph.D.)Bachelor's Degree in Electrical Engineering, Physics, Chemistry, Materials Science or in a STEM related Field.
• Experience in project/program management and/or TFT lead.
• Experiencein serving external Foundry customers through technicalinteractions.
• Experiencein GAA (Gate-All-Around) technology architecture and understanding on GAA-specific defect issues.
• Experience with module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits