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Innovate and Design:Architect and design innovative High-Speed IO like PCIE, C2C, CXL etc for complex silicon designs to improve quality, safety, perf/power, validation methodology and manufacturability; Ensure interoperability with connected devices and system components in complex interconnect topologies.
Push the Boundary:Define roadmaps by tracking industry/market trends, collecting current product feedback, prototyping new ideas, and conducting data-driven tradeoff analysis.
What We Need To See:
BS or MS degree in Electrical/Computer Engineering or equivalent experience.
8+ years working in HSIO development, bringup planning, HSIO SerDes, protocol, functional and electrical validation, and/or power optimization
Experience with HSIOs likePCIE/CXL/USB/UFS/MGBEetc or chip-to-chip interconnects including understanding of process/temp/voltage sensitivity on BER.
Excellent experience with identifying full chip data paths for HSIO saturation and working with applications to stress test for stability.
Experience with system level and interconnect power management optimizations.
Strong EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting.
Deep understanding of firmware/driver structures and their interaction with HW.
Hands on with Lab test and measurement equipment is a plus.
Excellent verbal communication and written, presentation skills.
Effective in a collaborative environment.
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