Lead multiple networking ASIC product engineering activities, including real-time decision-making on silicon quality, defining pass/fail screening criteria, solving multi-disciplinary challenges, and improving cost and quality through data analysis and deep testing and hardware expertise.
Collaborate closely with vendors (test houses and fabs) and internal engineering teams, including operations, IC test, reliability, characterization, package assembly, and hardware teams.
Drive interactions with wafer fabs and OSATs, ensuring key quality metrics are met.
Oversee volume ramp and mass production through test program releases, data analytics, lot disposition, test time optimization, yield improvement, and RMA handling.
Work with cross-functional teams across the globe, including ATE and SLT Test Engineering, Q&R, Packaging, Supplier Management, and Operations to build and maintain high-volume manufacturing screening solutions.
Bachelor’s degree in Electrical Engineering, Materials Engineering, or Physics.
At least 5 years of experience in semiconductor manufacturing or related fields.
Strong analytical skills with the ability to identify trends, patterns, and insights from data.
Knowledge of advanced semiconductor technologies and trends.
Experience working with ATE tools.
Strong communication skills with the ability to lead without formal authority.
Experience with data reporting and visualization tools such as Power BI.
Ability to multi-task, collaborate effectively, and solve problems proactively.
Experience in semiconductor industry, IC Product Engineering, and advanced packaging.
Background in complex and large-scale data/yield analysis.