Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or in a related technical field, or equivalent practical experience.
3 years of experience designing Register-Transfer Level (RTL) digital logic using SystemVerilog for FPGA/ASICs or equivalent practical experience.
3 years of experience in Application-Specific Integrated Circuit (ASIC) digital design, including SystemVerilog, scripting languages and synthesis.
Preferred qualifications:
Master's Degree or PhD in Electrical Engineering, Computer Science, or in a related technical field.
Understanding of computer architecture including industry standard interfaces and memory subsystems.
Knowledge of accelerators like Machine Learning (ML), or Graphics Processing Units (GPU) or similar high performance designs.