Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in Design Verification.
4 years of experience in people management, developing employees.
Experience constructing reusable verification components and environments using Universal Verification Methodology (UVM), System Verilog or similar.
Experience in Portable Stimulus Standard (PSS), formal or emulation based SimXL methodologies.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.
Experience in one or more of the following like Operating Systems, Memory Management, Caches Hierarchies, Coherency, Memory Consistency Models, Memory Ordering, Double Data Rate (DDR)/Low Power Double Data Rate (LPDDR), Peripheral Component Interconnect Express (PCIe), or Packet Processors.
Experience working with software teams to define hardware/software interfacing including control/status registers, security, and error handling.
Experience with Formal verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
Experience building verification methodologies that span simulation, emulation and Field Programmable Gate Array (FPGA) prototypes.