Expoint - all jobs in one place

Finding the best job has never been easier

Limitless High-tech career opportunities - Expoint

Google Senior Design Verification Engineer Mixed Signal Silicon 
Taiwan, New Taipei 
838804793

25.09.2024

Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
  • Experience developing and maintaining verification testbenches, test cases, and test environments.

Preferred qualifications:
  • Experience in one or more scripting languages (e.g., Python, etc.).
  • Experience with RTL, low power (e.g., UPF/CPF), gate level (e.g., GLS) and formal verification techniques.
  • Experience creating/using verification components and environments in methodology (e.g., UVM, VMM, OVM).
  • Experience working with mixed signal (e.g., AMS/DMS) designs and mixed mode verification.
  • Experience in writing SystemVerilog models of analog blocks using advanced techniques (e.g., Real Number Modeling (RNM), Verilog-AMS, etc.).
  • Experience in creating detailed block-level design verification strategies and plans.