Cisco Physical Design Engineer 

United States, Massachusetts 

838530793

The application window is expected to close on: 8/15/25.

Job posting may be removed earlier if the position is filled or if sufficient number of applications are received.

You will collaborate with Acacia’s ASIC and Hardware teams in the engineering organization to deliver tape-out quality physical designs.

You will work closely with RTL designers to debug and root-cause physical implementation issues related to design, tools, etc. and arrive at a feasible solution through the augmentation of input and design collateral.

You will work closely with Back-end team on timing signoff for seamless physical design closure.

You will work with the ASIC physical design team to enhance and continuously improve the physical design implementation flow.

• BS in Electronics/Electrical Engineering or equivalent with 5+ years of experience in the telecommunications industry
• At least 5 years of professional engineering experience, including experience in advanced technology nodes: 5nm, 5/4nm, 3nm, and below
• Experience with industry standard CAD methodologies from Cadence, Synopsys and/or Mentor
• Experience with floor planning & partitioning, synthesis, place & route, static timing analysis (STA), formal equivalence check, Clock Tree Synthesis, timing closure, signal integrity, physical verification DRC/LVS
• Scripting experience with TCL, Python and Perl
• Execution of ASICs from product definition to production release

• Experience with power analysis, electromigration, IR signoff, process corner decisions, power grid analysis.
• Ability to manage stakeholders across analog and digital teams while interfacing with EDA vendors on issues/features/enhancements.
• Solid analytical, communication and presentation skills
• Self-motivated and the ability to drive without supervision.