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Google Physical Design Engineer United States, California, Sunnyvale 83718092
31.07.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 2 years of experience in ASIC physical design and methodologies in advanced nodes.
- Experience with ASIC physical implementation steps (i.e., synthesis, floorplanning, place and route, static timing, power and clock distribution, CDC, LEC, physical verification on blocks, sub systems, or full chip).
Preferred qualifications:
- Experience solving physical design challenges across various technologies (e.g., embedded processors, DDR, networking fabrics, etc.).
- Experience collaborating cross-functionally to design architecture by driving feasibility studies to explore power, performance and area tradeoffs.
- Experience in extraction of design parameters, QOR metrics, and analyzing trends.
- Experience in IP integration (e.g., memories, IO’s, and Analog IP).
- Knowledge of semiconductor device physics and transistor characteristics.
- Knowledge of Verilog/System Verilog Experience with leading one or more aspects of physical design.
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