Amazon Sr SOC Design Engineer - STA Hardware Compute Group 

United States, California, Sunnyvale 

825772579

Work hard. Have fun. Make history.Roles & Responsibilities:
- Includes definition and development of signoff methodology and corresponding implementation solution
- Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs.
- Full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex, multi-clock, multi-voltage SoC.
- Streamlining the timing signoff criterions, timing analysis methodologies and flows.- Work for Systems and Architecture, SoC Integration, Verification, DFT, Mixed Signal, IP owners, Synthesis, Place & Route and other local/remote teams to address the design challenges in the context of timing sign-off.
- Concepts of CRPR, clock paths analysis and tweaks to meet timing.
- Multi Corner and Multimode analysis.
- Close timing at Signoff corners covering the entire modes, delay corners for cells and interconnects.

- Bachelor’s degree or higher in EE, CE, or CS
- 10+ years or more of practical semiconductor implementation experience
- Scripting experience with Perl, Python, tcl, shell and drive to automate flows
- Proficiency in chip front-end and back-end implementation tools such as Fusion compiler, Design Compiler, ICC2 or Innovus and Primetime, Tempus
- Must have good communication and analytical skills.
- Should be able to work closely with IP Design teams and Backend Physical Design teams across multiple sites.

- PhD in Computer Science, Electrical Engineering, or related field
- Experience with memory compiler
- Experience with formal equivalence – Cadence Conformal/Synopsys Formality
- Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification
- Experience with DFT and DFM flows