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Google Chassis Power Architect Silicon United States, California, Mountain View 825642038
26.06.2024
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Info Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 6 years of experience in power optimization workflow.
- Experience with silicon power optimization methods and techniques.
- Experience with power management IPs.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in post-silicon power calibrations and debug.
- Experience in low power design including UPF/CPF, multi-voltage domains, power gating, and on chip power management IP design.
- Experience in using Electronic Design Automation (EDA) tools, such as Conformal LP, Power-Artist, DC/RC, PT/PTPX, Incisive/VCS.
- Experience in design and analysis of full chip power, with an understanding of clock, reset, and power sequencing interactions.
- Understanding of ASIC design flows and methodology.
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