Intel Signal integrity intern 

China, Shanghai 

824375780

Minimum qualifications: � Must have an MS (with minimum 1+ years SI experiences) or PhD in Electrical Engineering or Electrical and Computer Engineering � Proved experiences on silicon, package and board level signal integrity.� Board-level system architecture, I/O structures topologies� Package, Printed Circuit Board (PCB) design and layout process and methodology � Experience with signal integrity modeling tools, including 3D EM modeling (Ansys HFSS) and simulation (Agilent ADS or similar) software� Experience with signal integrity analysis tools (ex: HSPICE, Sigrity tools, etc)� Lab hands on experiences on TDR, VNA, BERTscope, digital scopes, logic analyzers, and multi-metersStudent / InternShift 1 (China)PRC, ShanghaiPRC, Beijing, PRC, Shenzhen

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.