Nvidia Chiplet Physical Design Engineer 

United States, Massachusetts 

822705008

What you'll be doing:

• Be part of a cross-business-unit team and own the high-speed IP integration.

• Build a Chiplet floorplan layout design from early assembly/planning through implementation and signoff.

• Work closely with partition owners and Full Chip STA engineers to assure high quality and timely convergence.

• Define and implement efficient, high-quality Chiplet level physical design tools, flows, and methodologies.

• Gain hands-on experience implementing the partition-level BE design (RTL2GDS).

What we need to see:

• Great teammate

• BSEE / MSEE or equivalent experience.

• 8+ years experience in physical design

• Experience in unit and top-level floor planning, bump and RDL layout, full-chip clock tree, power grid planning, and DRC/LVS.

• In depth knowledge of physical design flows and methodologies (PNR, STA, physical verification).

• Deep understanding of all aspects of Physical construction and Integration.

• Knowledge in Physical Design Verification methodology LVS/DRC.

• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)