ARM Principal RTL Design Engineer - Cache Coherent Interconnect 

United States, Texas, Austin 

820925273

Arm System IP enables designers to build Arm AMBA systems that are high performance, power efficient and reliable. Configurable for many different applications, System IP is the right choice for your system whether it is a high-efficiency IoT endpoint or a high-performance server SoC.

As an RTL Design Engineer, you would be responsible for one or more functional units of the Interconnect while working closely with performance modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals.

An ideal candidate will have at least 10 years of work experience in microprocessor, SoC, memory controller and interconnect IP design.

• Understanding the high-level specification and requirements of functional units of Interconnect products.
• Define the Micro-architecture for an unit
• Develop Verilog RTL logic design for the unit
• Collaborate with verification team on the test plan development for the blocks and verification closure
• Debug functional or performance issues with the RTL using simulation and debug tools
• Analyze synthesis/timing reports, identify and address critical areas to meet the PPA targets

• BS/MS in Electrical and/or Computer Engineering with over 10 years of experience.
• Experience with interconnect and bus architectures (with proficiency in IO acceleration, PCIe, system caching, QoS)
• CPU or compute subsystem memory micro-architecture.
• Knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI) is a plus.
• Experience with Verilog or VHDL, coupled with design synthesis targeted to achieve specified frequency, power, and area targets
• Processor system knowledge including basic understanding of SoC systems as well as operating system software

• Prior verification, CAD and/or infrastructure experience.
• Experience with formal verification and physical design principles and methodologies.