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Cisco ASIC STA Engineer United States, California, San Jose 81932192
18.11.2024
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The application window is expected to close on 11/29/2024
What You'll Do
- This role expects you to be responsible for closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while managing ECO tasks.
- Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA, along with advising the Physical Design team on best practices.
- Additionally, you’ll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.
Who you’ll work with
You will collaborate with ASIC Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll be working closely with the timing lead on backend timing signoff, including CDC checks, static timing verification, and silicon debugging.
Who You Are
- Experience in generating timing constraints and performing quality checks such as setup, hold, transition, and noise.
- Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery.
- Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates
- Proficient in synthesis constraints and using industry standard synthesis tools.
- Good written and verbal communication skills.
- Collaborative and team-focused with the commitment to learn and grow.
Minimum Qualifications
- Bachelor’s degree in electrical or computer engineering (or other equivalent field) with 5+ years of related work experience.
- Prior experience using Synthesis Tools: Synopsys DC/DCG/FC.
- Prior experience in Static Timing Analysis & ECO: Synopsys Primetime/Cadence Tempus.
- Prior experience with scripting such as TCL, Perl, or Python.
Preferred Qualifications
- Master’s degree in electrical or computer engineering (or other equivalent field) with 2+ years of related work experience.
- Experience using: Synopsys PTPX/Tweaker/PrimeClosure
- Experience using Formal Verification: Synopsys Formality and Cadence LEC.
- Experience using Parasitic Extraction: Synopsys Star-RCXT, Cadence Quantus.
We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another – from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that).
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