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Apple CPU Design Timing Engineer United States, California 818160170
13.06.2024
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Description
As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project. RESPONSIBILITIES INCLUDE BUT ARE NOT LIMITED TO- Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency.- Work extensively with CPU micro-architects and Implementation engineers to drive timing closure for the CPU.
Key Qualifications
- Minimum BS and 3+ years of relevant industry experience
- Proficiency in static timing tools and methodology including familiarity with handling multiple clock and power domains, cross talk, noise, OCV, etc
- Prior experience performing timing analysis in high speed digital designs such as CPUs or other similar designs is a plus
- Familiarity with physical design tools and methodology including logic synthesis, PnR, parasitic extraction, logic equivalence
- Knowledge about deep sub-micron technologies and scaling trends
- Familiarity with CPU microarchitecture including common fundamental timing paths
Education & Experience
Minimum BS and 3+ years of relevant industry experience
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $138,900 and $256,500, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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