Western Digital Principal Engineer VLSI Design Engineering 

Canada, British Columbia, Area H (Cultus Lake/Columbia Valley) 

81560593

Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.

In this position, the individual will be responsible for all aspects of digital design in NAND Flash memory, focusing on micro architecture, RTL design, verification, logic synthesis, and timing analysis to deliver a design meeting target power, performance and area goals.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• RTL design and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT, timing analysis and closure
• Balance design trade-offs with modularity, scalability, power, area, and performance.
• Interface with internal and external teams/customers to drive necessary technical specifications and features based on individual requirements
• Participating in Post-Si evaluation and debug
• Drive cross function support for productization
• Technical guidance and mentoring of junior engineers

REQUIRED:

• MSEE plus 6 years of relevant experience
• Experience with chip level integration, chip lead, and full product life cycle (requirements, design, implementation, test) of Logic design
• Working knowledge of the entire Logic design flow from RTL to GDSII (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion, place-and-route, clock tree synthesis, extraction, static timing analysis, physical verification)
• Working knowledge of NAND flash memory cell device operations, algorithms for program/read/erase
• Excellent communication (written and verbal) and interpersonal skills

PREFERRED:

• Experience developing digital circuit designs for low power operating conditions
• Working knowledge of device physics and process
• Working knowledge of NAND Flash memory design including Analog, Core, Datapath and IO circuits
• Proficiency with following Digital design tools
  • Synthesis - Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler
  • Static Timing - Synopsys Primetime or Cadence Tempus
  • Place and Route - Synopsys ICC or Cadence Encounter or Innovus
• Familiarity with revision control tool and EDA standard formats used in cell/library development and modeling - Liberty (timing model), SDC (Synopsys Design Constraints)
• Programming experience in C, C++, Python or Perl

The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. Self-motivated and self-directed, however, must have demonstrated ability to work well with people. A proven desire to work as a team member, both on the same team and outside of the team. Ability to troubleshoot and analyze complex problems. Ability to multi-task and meet deadlines. Excellent communication (written and verbal) and interpersonal skills.