Microsoft Principal Silicon Design Engineer 

United States, California, Mountain View 

805087125

engineers to help achieve that mission.

Principal Silicon Design Engineer

AI Silicon Engineeringand industry knowledge to envision and implement future technical solutions that will manage andthe Cloud infrastructure.

Required Qualifications

• 9+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
• 6+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs related to arbitration and fabric logics for high-throughput/low-latency data transport.
• 6+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINT closure.
• 6+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug, Python script.

• to meet Microsoft, customer and/or government security screening requirementsarerequiredfor this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will berequiredto pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
• This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate willbe requiredto provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Additional Or Preferred Qualifications

• 15+ years technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.
• Track record of successful ASIC tape outs in deep sub-micron technologies
• Deep understanding of the physical design impact for each micro-architecture and work closely with PD engineers to find the best tradeoff given the performance/area/power constraints.
• Experienced on a variety of micro-architecture areas such as Complex Control Paths, Memory hierarchies and standard industry interfaces such as Advanced extensible Interface (AXI).
• 5+ years of experience in designing complex control logics on Network-On-Chip(NOC) ASICs
• Ability and willingness to adapt and lead/work on a variety of designs.
• Experience of working on high-speed Network-on-Chip design from architecture through tape-out.

Microsoft will accept applications for the role until February 13, 2025.

You will be part of the design team driving manyof high performance, high bandwidthin the start-of-the-art AI SoCs. The tasks will include working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, synthesis, and System on Chip (SOC) integration on different subsystems. Throughout the program you will be interacting with various teams, including architecture, verification, and physical design, ensuring that the design is implemented and verified to the spec.

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