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Apple Formal Verification Engineer Germany, Bavaria, Munich 795040528
28.03.2024
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Key Qualifications
- Required Qualifications
- Interest in learning and becoming an expert in SoC/CPU/GPU/Cellular designs, VLSI, and digital logic design and verification techniques
- Detail oriented mindset and desire to overcome challenges is required
- Desirable Qualifications
- Formal Method or Formal Verification technologies experience and abstraction techniques
- Knowledge and experience in interpreting hardware specifications and using
- Temporal logic assertion-based languages such as SVA or PSL
- Experience in using EDA formal tools and tool development experience is a plus
- Proficiency in any scripting language with excellent debugging skills
- Extraordinary teammate with excellent interpersonal skills
- Passionate about developing world-class/innovative formal verification solutions
Description
As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP’s (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.), you will be responsible for: Working with Apple Silicon's world-class SOC and IP design engineers to develop a formal micro-architecture specification. Developing comprehensive formal verification test plan. Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture. Crafting novel and creative solutions for verifying complex design micro-architectures. Developing and implementing re-usable and optimized formal models and verification code base. Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.
Education & Experience
BS / MS / Ph.D in EE or CS is required.
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