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Apple High Speed Analog/Mixed-Signal IC Design Engineer United States, California, Cupertino 793499843
02.05.2024
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Key Qualifications
- Proven track record in high-speed analog/mixed-signal architecture and circuit design and productization
- Deep understanding of PLL and clocking fundamentals and solid understanding of phase noise, jitter analysis/budgeting and loop dynamics
- Demonstrated innovation, self-learning, leadership skills, and a growth mindset throughout your career
- Excellent teamwork and productivity/scripting skills
- You are expected to have a proven track record in one or many of the following:
- Design of High speed PLL and clocking circuits: RO/LC oscillators, drivers, phase interpolators, dividers, TDC, DTC, and reference circuits
- Design/debug RTL of algorithms and functions for Digital PLLs
- Develop System Verilog models and perform behavioral simulations to investigate new clocking architectures’ performance and function
Description
Given your high aspirations, we expect you to apply your expertise to the development of PLL and clocking architectures and circuits for diverse applications including SoC, SerDes, CPU and Cellular applications.
Education & Experience
BSEE with preferred 8+ years of relevant experience.
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $170,700.00 and $300,200.00, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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