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What you'll be doing:
Build the prototype by making the RTL FPGA friendly, partition the design, synthesis, place and route.
RTL design and verification of FPGA transactors.
Improve the performance and generate bit streams.
Bring up the design on board and indulge in problem solving.
Release the prototype to the customers and support them when they face problems.
You are expected to understand the design and implementation, define the configurations, develop/modify the infrastructure, and verify the correctness of the design.
Good coordination with architects, designers, verification engineers, and SW teams will be needed to accomplish your tasks.
What we need to see:
BS/MS with proven experience, or equivalent experience.
3+ years experience in FPGA prototyping tools like Protocompiler, Synplify Premier, Vivado and ASIC flows. Exposure to various FPGA devices.
Expertise in Verilog, System Verilog.
Experience in Backend flows of FPGA Prototyping - Synthesis, P&R and Timing closure.
Exposure to ASIC design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi, GDB).
Good digital design concepts.
Good debugging and problem solving skills.
Hands on with lab FPGA debug methodologies, such as Protocompiler debug, ChipScope, SignalTap or others.
Hands on experience with lab debug equipment, such as oscilloscopes and logic analyzers.
Ways to stand out from the crowd:
Good interpersonal skills and ability & desire to work as a phenomenal teammate.
Experience in system/SOC/Full chip level verification desirable.
Prior experience with hardware emulation or prototyping (Synopsys HAPS, Zebu, Cadence Protium, Palladium, Mentor Veloce) of a high-performance processor or SOC is a plus.
Scripting knowledge (Perl/shell/Tcl) is desired.
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