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Google IP Design Verification Silicon 
India, Karnataka, Bengaluru 
780429291

05.08.2024
Minimum qualifications:
  • Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
  • 2 years of experience creating and using verification components and environments in standard verification methodology.
  • Experience designing or verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog for FPGAs, ASICs, or SOCs.
  • Experience creating/using verification components and environments in methodology (VMM, OVM, UVM).

Preferred qualifications:
  • Experience with Interconnect Protocols (e.g., ACE, CHI, CCIX, CXL).
  • Experience with Verification Techniques.
  • Experience with performance verification of ASICs and ASIC components.