Bachelor's degree in Electrical or Electronics Engineering or equivalent practical experience.
8 years of experience in DFT Methodologies.
Experience with DFT Electronic Design Automation (EDA) tools like Tessent.
Experience with Automatic Test Pattern Generation (ATPG), Low Power designs, Built-In Self Test (BIST), Joint Test Action Group (JTAG), Internal Joint Test Action Group (IJTAG) tools and flow.
Preferred qualifications:
Experience architecting/developing DFT flows and methodologies.
Experience in collaborating with Design, Physical Design (PD) and Static Timing Analysis (STA) teams.
Excellent scripting skills in languages like Python and TCL.