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Intel ASIC Flow Methodology Lead India, Karnataka, Bengaluru 777158341
29.04.2025
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Job Description:
- Development and support of ASIC tech files and development of ASIC flows/methodologies. Enabling APR tools for placement/routing and Timing at Intel advance new process node. physical designs (RTL to GDSII) of test vehicles to evaluate developed tech files and APR flow/methodology.
- Regular Interaction with Stakeholders including vendors during tech file and flow development. Timely tracking of issues and resolving customer support issues.
- Write good documents for ASIC flows and PDK.
- Train the users and design engineers on ASIC flows and tech file usage.
- Debug the complex design issues and help the design and CAD teams in PDK and flow deployments. support in APR/STA tool certification.
- BTech/BE in EE/CS with minimum 10 relevant industry experience OR MTech in EE/CS with minimum 8 years relevant industry experience OR Ph.D. in EE/CS with minimum 5-year relevant industry experience in the following areas:
- Experience in ASIC PDK kit/Physical design/ ASIC Design automation role.
- Hands-on experience with Synopsys and Cadence Place and Route tools, Timing tools, Floor planning, IR Drop and Physical verification.
- Should have good understanding of Verilog. Exposure to low power techniques and PPA analysis.
- Good understanding of 3D IC flow methodology will be added advantage. Knowledge of TCL and PERL scripting is a must.
- Strong presentation and communication skills. Team oriented and ability to work independently and bring new initiatives.
- Good in stakeholder management and should be detailed oriented.
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