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Intel NM Process integration defect reduction yield engineer United States, New Mexico, Albuquerque 776421791
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The NM DMO Yield Department is looking for process integration and defect reduction engineers to support interconnect and advanced packaging semiconductor chip fabrication. Engineers in the NM DMO Yield Department will support Fab 11X and Fab 9 for roles in Foveros, EMIB, Die Prep, Sort, Wafer Level Assembly, and Advanced Packaging. You will partner with all areas of the Yield Department including integration, defect reduction, quality and reliability, device analysis, and yield analysis. Process integration and defect reduction engineers are responsible for sustaining semiconductor fabrication process health on products moving from development to high volume manufacturing while designing and implementing improvements for yield, cost, and defects.
The NM DMO Yield team seeks engineers who enjoy problem solving, data analysis, and leading and participating in cross organizational teams. In this role you will plan and conduct experiments and data analysis to optimize and characterize new fabrication processes and understand sources of variation within the fab. You will be responsible for controlling technology change introduction, monitoring in line defect and parametric performance and end of line die yields, finding root cause for processing excursions and navigating fixes. In addition, yield engineers will receive new products from TD and ensure they are capable of high volume manufacturing while also driving improvement to quality, reliability, cost, yield, productivity and manufacturability.
The following skills are needed to be successful in this role:
Creative mindset resulting in the ability to propose novel mechanisms and solutions.
Strong analytical and data analysis skills to identify meaningful correlations and signals in large datasets.
Understanding of inline detection to identify rogue equipment, identify defect and parametric issues, and predict end of line yield impacts.
Project management skills to execute roadmaps that drive defect/yield/efficiency/cost improvements based on both known impact and program risk factors.
Capable of understanding and implementing process control monitoring strategies to detect out of control events which require intervention.
Can create strong responses to quality events to allow 24/7 disposition during preliminary, ramp, and high-volume stages of product lifecycle.
Full time onsite is required during training (estimated 6 months). After training, hybrid "work from home" to be defined by manager and employee, but continued onsite will be required. Role is not eligible for full time remote work.
Minimum Qualifications:
Must have a Bachelor's or a Master's degree in chemical engineering, Electrical Engineering, Mechanical Engineering, Material Science, Microelectronics Engineering, Chemistry, Physics or related field.
This position is not eligible for Intel immigration sponsorship.
Preferred Qualifications:
Demonstrated capability working in a high performing team culture which includes excellent teamwork and leadership skills, demonstrated problem solving and prioritization skills.
Fundamental understanding of semiconductor process flow
Experience with design of experiments (DOE) principles.
Experience in high volume manufacturing (HVM)
Experience in data analysis and statistical process control (JMP, SQL, PCS).
Understands concepts of statistical process control (SPC), process capability, true spec, and variance
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