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Google ASIC Design Verification Engineer Google Cloud United States, California, Sunnyvale 765498024
29.07.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- Experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
- Experience with SystemVerilog (i.e. SystemVerilog Assertions or functional coverage).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
- 6 years of experience in design verification.
- Experience with one or more of the following: networking, switching, congestion control protocols, PCIe, TCP/IP, RDMA, NVMe, or ARM interconnect protocols.
- Experience in Power aware verification, Gate level simulations, and Post silicon bring-up.
- Experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog for Application-Specific Integrated Circuits (ASICs).
- Familiarity with ASIC standard interfaces and memory system architecture.
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