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Google CAD Methodology Engineer Front-End India, Karnataka, Bengaluru 763937452
26.06.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer science, or equivalent practical experience
- 3 years of experience with development projects in VLSI
- Experience in RTL design, verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation
Preferred qualifications:
- Master’s degree in Computer or Electrical Engineering
- Experience in designing or verifying digital logic using SystemVerilog for FPGAs, ASICs, and/or SoCs
- Experience in design verification technologies like UVM, simulation, coverage collection, test planning, debug, integration flows, build/release flows
- Experience in programming languages such as C++ and scripting languages such as Python/Perl/TCL
- Experience in interacting with Electronic Design Automation (EDA) vendors and understanding of some of the EDA design tools like VCS, Xcelium, Verdi, Spyglass, Coretools, Defacto/Magillem
- Excellent scripting skills in Python, Perl, and TCL
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