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Job Area:
Engineering Group, Engineering Group > Hardware Engineering
Job Role
Work with multiple SOC Design teams to rollout robust DFTCAD flows for DFT logic insertion and DFT logic signoff.
Provide implementation flows support and issue debugging services
to SOC design teams across various site
enhancement routines
Should lead implementation flow development effort independently by working closely with design team and EDA vendors
Should drive new tool evaluation, methodology refinement for PPA optimization
Skill Set
Proficiency in Python/Tcl
Familiar with tools Tessent, TestMax, DC_NXT, FC , LEC, CLP signoff tools
Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking
Familiarity with standard software engineering practices like Version
Control, Configuration Management, Regression is a plus
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
3 to 6 years of experience in RTL/Netlist DFT insertion, Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Signoff
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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