Intel IP Design Verification Engineer 

India, Karnataka, Bengaluru 

76170399

BE/ME/MTech/MS with 6 to12 years of SerDes RTL verification experience.Must be well versed in using advanced verification methodologies like UVM/OVM/VMM/System Verilog, constrained random stimulus generation, assertion based verification and functional coverage techniques.Must be well versed in RAL standards, NLP/GLS verification flows. Experience in IP level and sub-system level verification on protocols like PCI-E , UCIe, HBM, UFS is a strong plus.Having relevant experience in enabling and verifying controller interoperability testing at sub system level is a plus.Familiarity with RTL design aspects like Physical Coding sub layer, Physical media access blocks is a strong plus.Basic familiarity with high level advanced receiver adaptation techniques which may include fsm or ucontroller based firm- ware driven equalization is a strong plus.Basic Knowledge of real value modelling of channel impulse response for receiver adaptation / equalization verification is a strong plus.We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits