Intel DFT Architect/Engineer 

United States, Texas, Austin 

760360441

The NSS team is looking for a Senior DFT Architect/Engineer that can help plan the architecture for the most efficient DFT solution with the highest coverage. The team member would be responsible for the holistic DFT solution for the SOC with the skills listed below:

• Insertion of DFT structures, generation, simulation, and validation of test patterns for both DFT logic verification and for High Volume Manufacturing (HVM) testing of the design.
• Understanding of Static Timing Analysis (STA) constraints for physical construction and timing closure in all DFT modes as well as collaboration with the Structural Design team to achieve timing closure.
• Understanding of DFT architectural decisions to ensure the highest quality and most efficient DFT solutions.
• Static Timing Analysis, like Synopsys Primetime, capability of constraint and timing path debug

In this role, your daily agenda will be anything but ordinary. On a regular basis, you will:

• Develop the logic design, register transfer level (RTL) coding, simulation, and provide DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).
• Participate and collaborate in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).
• Develop HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).
• Apply various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
• Optimize logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, andtest time/vector memoryreduction goals as well as design integrity for physical implementation.
• Review the verification plan and drive verification of the DFT design to achieve desired architecture and microarchitecture specifications.
• Ensure design features are verified correctly and resolve and implement corrective measures for failing RTL tests to ensure correctness of features.
• Integrate DFT blocks into functional IP and SoC and support SoC customers to ensure high-quality integration of the IP block.
• Collaborate with post-silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
• Drive high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develop HVM content for rapid bring up and production on the ATE.

Minimum Qualifications

• Bachelor’s degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field of study.
• 5+ years of experience with SOC DFT principles for SCAN for logic testing, BIST and repair for memory test, Boundary SCAN
• Experience in Test insertion, pattern generation, and validation
• Experience with Industry standard DFT tools such as Siemens Tessent DFT, Synopsys DFT Compiler, DFTMax, TetraMax, or similar
• Experience with Industry standard Static Timing Analysis tools such as Synopsys Primetime or similar

Preferred Qualifications

• Post graduate degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field of study.
• Experience with IEEE1149 BSCAN and IEEE1687 IJTAG or similar
• Experience with DFT architecture development and planning for an SOC.
• Programming skills
• Experience with DFT integration of IP (e.g. DDR, SerDes, PLLs)
• Unified Power Format (UPF) verification experience

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits