Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post silicon on the quality of validation done during presilicon development, updates test plan for missing coverages and proliferates to future products. This posting is for SOC Pre-Silicon OOBMSM Validation.
Qualifications:Minimum Qualifications: BE/Btech/MTech with 5 Plus years of experience
Preferred Qualifications:
Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.OVM/UVM, System Verilog, constrained random verification methodologies.The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.Create plans and tests for validating portions of a complex microarchitecture using written specs, RTL code, Firmware and other tests as a guideDevelop and utilize various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid designParticipate in the debug of failures on silicon and develop new testing strategies to detect these failures on RTL modelsPre-Silicon OOBMSM Verification knowledge will be an added advantage.
Experienced HireShift 1 (India)India, Bangalore
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
