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Google ASIC Engineer IP Design Silicon India, Karnataka, Bengaluru 753430217
14.04.2025
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Minimum qualifications:
Preferred qualifications:
- Bachelor’s degree in Electrical/Computer Engineering or equivalent practical experience.
- 3 years of experience with Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture and automation.
- Experience with RTL design using Verilog/System Verilog and microarchitecture.
- Experience with a scripting language like Python or Perl.
Preferred qualifications:
- Master's degree in Computer Science or Electrical Engineering.
- 6 years of industry experience with IP design.
- Experience with methodologies for low power estimation, timing closure, and synthesis.
- Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).
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