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What you'll be doing:
Build FPGA prototypes by making RTL FPGA-friendly, partitioning the design and taking it through synthesis and place and route.
Improve performance of the prototype, analyze timing and generate bit streams.
Bring up the design on FPGA prototyping platforms and indulge in problem solving.
Release the prototype to the customers and support them when they face problems.
You are expected to understand the design and implementation, define the configurations, develop/modify the bringup and testing infrastructure and verify the correctness of the design.
Good coordination with architects, designers, verification engineers, and SW teams will be needed to accomplish your tasks.
What we need to see:
BS (or equivalent experience) in Electrical Engineering, Computer Engineering, or related fields with 7+ years of experience, or MS with 5+ years of proven experience in FPGA prototyping.
Good understanding of FPGA prototyping architecture, devices, flows and tools.
Experience in backend flows of FPGA Prototyping - Synthesis, P&R and Timing closure, with emphasis on Synopsys Protocompiler or Synplify Premier and Xilinx Vivado
Exposure to ASIC design and verification tools (VCS or equivalent, Verdi, GDB).
Knowledge of Verilog, System Verilog and digital design concepts.
Good debugging and problem solving skills.
Hands on experience with lab FPGA debug methodologies, tools (Identify or ChipScope), and lab debug equipment (oscilloscopes, logic analyzers).
Ways to stand out from the crowd:
Scripting knowledge (Perl/shell/Tcl) is desired.
Good documentation, communication and interpersonal skills.
Experience in system/SOC/Full chip level verification desirable.
Prior experience with hardware emulation or prototyping (Synopsys HAPS, Zebu, Cadence Protium, Palladium, Mentor Veloce) of a high-performance processor or SOC is a plus.
You will also be eligible for equity and .
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